Camera system and photographing lens thereof

ABSTRACT

A camera system includes a camera body and a photographing lens which is detachably attached to the camera body. The photographing lens has an input and output device which inputs and outputs data to and from the camera body, a timing controller which outputs clock pulses for driving the input and output device, and a loading device which loads specific initial value lens data in the input and output device in accordance with the clock pulses. The camera body includes an information processing device which receives the specific initial value lens data loaded in the input and output device.

This application is a continuation of application Ser. No. 07/691,976, filed Apr. 26, 1991, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a camera system having a signal communication function between a camera body and a photographing lens and an improved photographing lens thereof.

2. Description of Related Art

In a recent single lens reflex camera having an automatic focusing device, information peculiar to a photographing lens, such as open F-number data used in an automatic exposure function or an automatic focusing function, is sent as electrical signals from the photographing lens to a CPU (central processing unit) associated with a camera body.

Information peculiar to the photographing lens is stored in a lens ROM provided in the photographing lens. The photographing lens and the camera body are provided with electrical contacts on a lens mount and a body mount to transmit and receive the signal information between the photographing lens and the camera body, respectively. The body CPU transmits and receives the signal information to and from the lens ROM through the electrical contacts and reads the data stored in the lens ROM. A clock pulse is output from the camera body to send address signals from the body CPU synchronously therewith, so that predetermined data can be read out from the lens ROM in accordance with the address signals. The reading of the data from the lens ROM is carried out in accordance with a serial communication that is controlled by the body CPU. The body CPU can not simultaneously perform other operations in real time during this communication.

Furthermore, in the case of a photographing lens having an AF motor (automatic focusing motor) and a PZ motor (power zoom motor), etc., if the control of these motors is affected by the body CPU, there is an overload on the body CPU. In particular, in a single lens reflex camera in which various kinds of photographing lenses are exchangeably mounted to one camera body, the body CPU must read different parameters, depending on the photographing lenses, from the associated lens ROMs and perform predetermined arithmetic operations in accordance with the read parameters so as to control the photographing lenses. This makes quick operations impossible, or next to impossible.

On the other hand, the provision of different lens ROMs for every photographing lens increases the manufacturing cost thereof.

It is desirable in a single lens reflex camera that if a novel camera body or photographing lens is newly developed, the new camera body or the new photographing lens can be used for an old type photographing lens or camera body, and vice versa.

SUMMARY OF THE INVENTION

The primary object of the present invention is to decrease the load of operations of a camera body side, to make it possible to set data of a photographing lens synchronously with a clock pulse outputted from the camera body, and to realize a novel camera system that is compatible with a conventional camera system.

To achieve the object mentioned above, according to the present invention, there is provided a camera system that includes a camera body, and a photographing lens that is detachably attached to the camera body, in which the photographing lens comprises means for inputting and outputting data to and from the camera body, a timing control means for outputting clock pulses for driving the input and output means, and means for loading specific initial value lens data in the input and output means in accordance with the clock pulses, the camera body comprising an information processing means for receiving the specific initial value lens data loaded in the input and output means.

With this arrangement, the photographing lens can set the specific initial value data asynchronously with the clock pulse from the camera body. Thus, it is unnecessary to set the specific initial value data at a constant time interval determined by the control of the camera body side. Accordingly, the time for adjustment on the photographing lens side can be increased, so that necessary operations, such as a calculation can be performed on the photographing lens side and the camera body side in the increased space of time.

According to another aspect of the present invention, a shift register is provided in the input and output means of the photographing lens. The timing control means comprises a clock generating means and a lens CPU. Upon transfer of the data to the camera body, the initial value data is first loaded in the shift register in accordance with the clock pulse from the timing control means. The loaded data is then serially transferred to the camera body. The data calculated by the lens CPU and outputted therefrom is loaded after the loading of the initial value data into the shift register. Consequently, the lens CPU performs the arithmetic operation independently of the transfer of the initial value data during the shifting of the initial value data in the shift register, decreasing the time necessary for transferring and processing the data.

The other aim of this invention is to offer a camera system, a camera body and photographing lens, in which either of the components can be attached to a former type of its partner and are able to interchange information with each other without passing through an input and output means after the completion of the process in which the photographing lens transfers specific initial value lens data to the camera body by its order through the input and output means.

According to the combination of the inventions above, a camera body and a photographing lens are enabled to interchange information with each other in a shorter period of time than before, because of the following fact:

Initial value data outputted from the photographing lens is not only transferred to the camera body through an input and output means in the same way as before, but in addition, the data can also be interchanged without passing through an input and output means.

A lens information processing means having a calculating function installed in the photographing lens calculates the variable lens data, some data of which can not be calculated by an information processing means installed in the camera body.

The present disclosure relates to subject matter contained in Japanese Patent Applications No. 02-110766 (filed on Apr. 26, 1990) and No. 02-117930 (filed on May 8, 1990) which are expressly incorporated herein by reference in its entirety.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described below in detail with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a single lens reflex camera having a camera system according to the present invention;

FIG. 2 is a block diagram of a main circuit arrangement of a camera body shown in FIG. 1;

FIG. 3 is a block diagram of a main circuit arrangement of a photographing lens shown in FIG. 1;

FIG. 4 is a more detailed block diagram showing a lens interface circuit shown in FIG. 1;

FIG. 5 is a block diagram of an I/O block of a lens interface circuit shown in FIG. 1;

FIG. 6 is a block diagram of a reset circuit of a lens interface circuit shown in FIG. 4;

FIG. 7 is a timing chart of operations of the reset circuit shown in FIG. 6;

FIG. 8 is a schematic view of a 24 bit shift register in a lens interface circuit;

FIG. 9 is a diagram of a first eight steps of a shift register and a data loading circuit in a lens interface;

FIG. 10 is a timing chart of data loading operations of the shift register of FIG. 8;

FIG. 11 is a timing chart of data communication of a camera system according to the present invention;

FIG. 12 is a flow chart of operations of an indication CPU of a camera body of the camera system of FIG. 1;

FIGS. 13A, 13B and 13C are flow charts of data input communication of an indication CPU of a camera body of the camera system of FIG. 1;

FIG. 14 is a flow chart of the main operation of a CPU of a photographing lens used with the camera system of FIG. 1; and,

FIGS. 15A, 15B and 15C are flow charts of a serial interruption for data communication of a CPU of the photographing lens.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a single lens reflex camera having a camera system according to an aspect of the present invention.

Camera body 1 has a main CPU 10 and an indication CPU 11. The main CPU 10 generally controls the whole camera system and performs arithmetic operations of various data necessary for taking a picture. The indication CPU 11 functions not only as an interface (data communication) to input data by switch members and to transmit and receive data (signals) to and from a photographing lens 2, but also as a controller to control the indication of the photographing data.

A light receiver 14, which receives light incident thereon through the photographing lens 2 and correspondingly outputs analog signals in accordance with the amount of light received, is connected to the main CPU 10 through an A/D converter 15. The indication CPU 11 is connected to an LCD panel 12 which indicates the photographing data and is also connected to a DX code input circuit 13 which selectively reads at least ISO sensitivity data of a film from DX codes provided on the surface of a parrone of the film.

The main CPU 10 is also connected to an exposure control circuit 16 which drives and controls a shutter mechanism (not shown) and a diaphragm mechanism (not shown), etc., in accordance with the input photographing data, a CCD processing circuit 18 which detects the focusing of the photographing lens 2 in response to data (i.e., focal point data) of an object to be taken (this data is outputted from an automatic focusing CCD object distance measuring sensor 17), an AF motor control circuit 20 which drives an AF motor 19, and an AF pulser 21 which detects the angular displacement of the AF motor 19 to generate pulses corresponding to the angular displacement. The object distance measuring sensor 17 receives light of the object which is divided into two or more light fluxes and is made incident through the photographing lens 2 to output a predetermined phase difference signal (defocus signal). The AF motor 19 drives a focusing mechanism 31 through a coupler 19a provided on a body mount BM of the camera body so as to project from the camera body and a coupler 31a provided on a lens mount LM of the photographing lens 2 when the connection between the couplers 19a and 31a is established to move groups of focusing lenses (not shown).

Battery 22 supplies power through the motors not only to the motors, electronic components and electronic circuits in the camera body 1, but also to the electronic components and electronic circuits in the photographing lens 2.

In the photographing lens 2 are provided a focusing mechanism 31 which rotates a focus adjusting cam ring (not shown) to relatively move the focusing lens groups in the optical axis direction, so as to affect a focusing operation, and a zooming mechanism 32 which rotates a zoom ring (not shown) to relatively move at least two groups of variable power lenses in the optical axis direction so as affect a zooming operation.

The focusing mechanism 31 is connected to the coupler 31a which is electrically connected to the coupler 19a when the photographing lens 2 is attached to the camera body 1 in order to transmit the rotational drive of the AF motor 19 to the focusing mechanism 31. The couplers 19a and 31a are disconnected from one another by a disengaging means (not shown), so that a photographer can manually rotate a focus adjusting operation ring to adjust the focus in the manual focusing mode.

The zooming mechanism 32 is driven by a zoom operation ring (not shown) which is in turn driven by a PZ (power zoom) motor 34, in the power zoom mode, and by the photographer, in the manual zoom mode, respectively. The PZ motor 34 is driven and controlled by a lens CPU 30 through a power zoom (PZ) motor driver 33 in the power zoom mode. The power zoom mode includes a manual power zoom mode in which power zooming is affected by the operation of a zoom switch SWZM2 (shown in FIG. 3), and a controlled power zoom mode in which zooming is automatically controlled in accordance with the determination of the lens CPU 30. The "controlled power zoom" mode referred to herein comprises a power zoom mode in which a focal length f at which a specific object is in focus is varied so as to keep the value of d/f (wherein d designates an object distance) constant when the object distance d changes. The power zoom mode and the manual zoom mode are selected by a switching means which is actuated by a zoom switch SWZM1.

To input ports of the lens CPU 30 are connected a PZ pulser 35 which detects the displacement of the PZ motor 34 and generates a predetermined number of pulses corresponding thereto, a distance code plate 36 which reads position data of a focus adjusting cam ring (i.e., focusing lens groups) driven by the focusing mechanism 31, a zoom code plate 37 which reads position data (i.e., focal length data) of the zooming cam ring (variable power lens groups) driven by the zooming mechanism 32, a zoom operation code plate 38 which inputs data of the direction and speed of the power zooming by the operation of the zoom operation switch, a lens judgement code plate 39 which determines the type of the photographing lens (i.e.; zoom lens, single focus lens, or single focus macro lens, etc.), and a K value input member 40 which inputs data of the K value at a telephoto extremity. In the illustrated embodiment, "K value" means the number of pulses of the AF pulser 21 that are necessary for moving an image plane formed by the photographing lens 2 through a unit displacement, but is not limited thereto.

The distance code plate 36 and the other code plates are per se known. Usually, these code plates are secured to a cam ring or cam rings and selectively connected to respective brushes having a plurality of electrical contacts which are brought into slideable contact with the codes (i.e.; conducting portions and non-conducting portions) of the code plates. The positions of the cam rings are detected as bit information by a combination of the codes with which the electrical contacts of the brushes come into contact. However, the data detecting mechanism is not limited to such a combination of the code plates and the brushes.

A lens interface 41 is connected to a data input terminal of the lens CPU 30. The data communication between the lens CPU 30 and the indication CPU 11 is effected through the lens interface 41 to which a macro code member 42 is connected, in order to input macro data thereto in the macro mode.

The lens CPU 30 performs the arithmetic operation to obtain various data, such as a present focal length, a present object distance, etc. The data (i.e.; program, algorithm, constant, etc.) necessary for the arithmetic operation is stored in an internal ROM 30a of the lens CPU 30 (shown in FIG. 3).

Circuit Of Camera Body

The circuit arrangement of the camera body 1 will be described below in detail with reference to FIG. 2.

The voltage of the battery 22 which is controlled by a regulator 23 and which is backed up by a super capacitor 24, is supplied to terminal VDD1 of the indication CPU 11. The indication CPU 11 is always activated at a constant voltage input to the terminal VDD1.

Terminal P1 of the indication CPU 11 is connected to a DC/DC converter 25, which turns the power source of the main CPU 10 ON and OFF. In addition, photometer switch SWS is selectively connected to the DC/DC converter 25 to be turned ON when a shutter button (not shown) is pressed by a half step. Furthermore, terminals P3 and P4 of the indication CPU 11 are connected to a release switch SWR which is turned ON when the shutter button is fully pressed and a lock switch SWL which is turned ON when a back cover (not shown) of the camera body is closed so as to hold the indication CPU 11 etc., into a photographable position, respectively.

The DC/DC converter 25 is actuated when the lock switch SWL is turned ON and when the photometer switch SWS or the release switch SWR is made ON, and in accordance with a command from the indication CPU 11 upon inputting the lens data from the photographing lens 2, to supply terminal VDD of the main CPU 10 with a reference constant voltage to thereby actuate the main CPU 10.

Furthermore, terminals P5, P6, P7, P8 and P9 of the indication CPU 11 are connected to a mode switch SWM, a drive switch SWDR, an exposure correction switch SWXV, an up-switch SWUP and a down-switch SWDN, respectively.

The indication CPU 11 operates in accordance with the operative and inoperative states of the switches SWM, SWDR, SWXV, SWUP, and SWDN. For instance, the exposure modes, which includes a programmed exposure mode, an automatic exposure mode, and a manual exposure mode, are selected in accordance with the operation of the mode switch SWM. Similarly, drive modes, which includes a single shot mode and a continuous shot mode, are selected in accordance with the operation of the drive switch SWDR. The selection modes can be varied in accordance with an operation of the up-switch SWUP and down-switch SWDN at the position in which the exposure modes or the drive modes can be selected.

The indication CPU 11 makes it possible to change the exposure value when exposure switch SWXV is turned ON. Namely, the exposure value can be increased and decreased in accordance with the operation of the up-switch SWUP and the down-switch SWDN, respectively.

The indication CPU 11 has a group of indication control terminals PSEG connected to an indicating LCD 12 through a bus line. The indicating LCD 12 indicates the necessary photographing data in accordance with command of the indication CPU 11 when the lock switch SWL is turned ON.

Seven terminals P10 through P16 of the indication CPU 11 are connected to electrical contacts Fmin1, Fmin2, Fmin3, Fmax1, Fmax2, A/M, and Cont provided on the body mount BM of the camera body, respectively. Terminal P18 of the indication CPU 11 is connected to a switch circuit 26.

The electrical contacts Fmin1, Fmin2 and Fmin3 function as communication terminals for data communication between the photographing lens 2 and the indication CPU 11. Namely, the electrical contacts Fmin1, Fmin2 and Fmin3 constitute a serial clock signal inputting and outputting terminal SCK, a data transmitting and receiving terminal DATA, and a reset signal outputting terminal RES, respectively.

Terminals P10, P11 and P12 of the indication CPU 11 are always pulled up within the indication CPU 11.

The output of the switch circuit 26 is connected to a terminal VBATT and functions as a switch for establishing and breaking an electrical connection between the battery 22 and the terminal VBATT in accordance with the level of the terminal P18. Terminal Gnd of the indication CPU 11 is connected to ground terminal Gnd of the battery 22.

The indication CPU 11 and the main CPU 10 communicate with each other through serial terminals SCK, serial-in terminals SI and serial-out terminals SO. In the data communication, data is transferred using command codes, as shown in Table 1 below. In Table 1, the left column represents data which is transferred from the indication CPU 11 to the main CPU 10, and the right column represents data which is transferred from the main CPU 10 to the indication CPU 11. These data are set based on the measurements of the object luminance and the object distance, etc. controlled by the main CPU 10.

                  TABLE 1                                                          ______________________________________                                         Indication CPU → Main CPU                                                                 Main CPU → Indication CPU                             ______________________________________                                         mode set data     display Tv, Sv data                                          drive set data    film sensitivity information                                 exposure correction set data                                                                     AF accommodation pulse                                                         number data                                                  lens CPU data,    AF return-completion code                                    set Tv, Sv data                                                                AF accommodation code                                                          AF return code                                                                 AF return pulse number data                                                    AF accommodation, return code                                                  ______________________________________                                    

Contact groups PA, PB, PC, PD, PE and PF of the main CPU 10 are connected to an A/D converter 15, the exposure control circuit 16, the CCD processing circuit 18, the AF motor control circuit 20, the AF pulser 21, and the DX code input circuit 13, respectively.

Terminal P20 of the main CPU 10 is connected to a first AF switch SWAF1, which selects an auto focus mode in which focusing is automatically affected by the AF motor 19 and a manual focus mode in which focusing is manually affected by a photographer. Terminal P2 of the main CPU 10 is connected to a second AF switch SWAF2, which switches the mode of the shutter release between a focus priority mode and a release priority mode. The first and second AF switches SWAF1 and SWAF2 are mechanically associated with each other, so that, for example, when the manual focus mode is selected by the first AF switch SWAF1, the second AF switch SWAF2 is switched to the release priority mode. Namely, one of the AF switches SWAF1 and SWAF2 is turned ON, the other is turned OFF.

Circuit of Photographing Lens

The circuit arrangement of the electrical system provided in the photographing lens 2 will be explained below, with reference to FIG. 3.

The lens mount LM of the photographing lens 2 is provided with electrical contacts VBATT, CONT, RES (Fmin3), SCK (Fmin1), DATA (Fmin2), GND, Fmax1, Fmax2 and A/M corresponding to associated electrical contacts provided on the body mount BM when the photographing lens 2 is attached to the camera body 1. Although the arrangement of the electrical contacts of the lens mount LM is not identical to that of the body mount BM (rearranged for the purpose of clarification), the electrical contacts of the lens mount designated are electrically connected to the corresponding electrical contacts of the body mount with the same reference numerals.

Contact VBATT on the lens side is connected to the PZ driver 33, so that the power of the battery 22 is directly supplied to the PZ motor 34 through the contact VBATT by the switching operation of the PZ driver 33.

The contacts Fmax1 and Fmax2 on the lens side also function as a steady information transmitting means for transmitting the maximum F-number data of two bits to the camera body, similar to those provided on an existing (old) AE lens. Namely, the contacts Fmax1 and Fmax2 on the lens side are grounded through the switches SWmax1 and SWmax2, so that maximum F-number (minimum diaphragm value) data is formed in accordance with a combination of the levels of the switches SWmax1 and SWmax2 depending on the combination of ON/OFF states thereof. The combinations of the levels of the contacts Fmax1 and Fmax2 on the lens side and the maximum F-number are for example as shown in Table 2 below.

                  TABLE 2                                                          ______________________________________                                         F N O.         F max2  F max1                                                  ______________________________________                                         22             0       0                                                       32             0       1                                                       45             1       0                                                       ______________________________________                                    

The A/M contact on the lens side has a function to send the auto/manual information of the diaphragm to the camera body 1 and is grounded through a selection switch SWA/M. The selection switch SWA/M is in association with the rotation of a diaphragm ring (not shown) of the photographing lens 2, so that when the diaphragm ring is in the auto position and the manual position, the selection switch is turned ON and OFF, respectively.

Contacts Fmin1, Fmin2, and Fmin3 on the lens side function not only as a steady information transmitting means for transmitting the open F-number information of three bits to the camera body 1, similarly to those provided on an existing (old) AE lens, but also as data communication contacts between the camera body and the photographing lens. The relation between the levels of the contacts Fmin1, Fmin2 and Fmin3 on the lens side and the open F-number is for example as shown in Table 3 below.

                  TABLE 3                                                          ______________________________________                                         F N O.   F min3        F min2  F min1                                          ______________________________________                                         1.4      0             0       0                                               1.7      0             0       1                                               2        0             1       0                                               2.5      0             1       1                                               2.8      1             0       0                                               3.5      1             0       1                                               4        1             1       0                                               4.5      1             1       1                                               ______________________________________                                    

To provide both the steady information transmitting function and the data communication function on the contacts Fmin1, Fmin2 and Fmin3 on the lens side, the contacts are connected to PNP transistors Tr1, Tr2 and Tr3, respectively. The PNP transistors Tr (Tr1, Tr2 and Tr3) are connected at the emitters thereof to the lens contacts Fmin1, Fmin2 and Fmin3, and at the bases thereof to the contact CONT through fuze portions H1, H2 and H3 so as to establish and break the connection, respectively. The collectors of the transistors are grounded. It is possible to provide the fuse portions H1, H2 and H3 between the emitters and the lens contacts Fmin (Fmin1, Fmin2 and Fmin3).

The indication CPU 11 causes the voltage of the contact CONT to drop to ground in order to obtain the open F-number data from the lens contacts Fmin1, Fmin2 and Fmin3. As a result, any transistor Tr to which the fuse portion is connected is turned ON, so that the emitter of the affected transistor which has becomes a high level "H" and the emitter of the transistor which has not been turned ON becomes a ground level "L". Namely, the transistors Tr are selectively turned ON or OFF in accordance with the connection of the fuse portions H1, H2 and H3 to change the level of the emitters thereof. Consequently, the three-bit open F-number data is output to the lens contacts Fmin1, Fmin2 and Fmin3.

Terminals CONT, RES, SCK, DATA and GND of the lens interface 41 are connected to the terminals CONT, Fmin3, Fmin1, Fmin2 and GND on the lens side, respectively.

The lens contact CONT is connected to the bases of the transistors Tr and to the terminal CONT of the lens interface 41, as mentioned above. The switching of the power supply from the terminal CONT of the lens interface is affected through the terminal RES (lens terminal Fmin3). After the data on the open F-number is transferred, when the terminals CONT and RES become levels "H" and "L" respectively, the power is supplied to the lens CPU 30.

Terminal VDDB of the lens interface 41 is connected to terminal VDD of the lens CPU 30 through a capacitor C2, so that a constant voltage supplied from terminal CONT of the camera body 1 is supplied to the lens CPU 30.

Terminals DIS1, DIS2 and DIS3 of the lens interface 41 are connected to distance code plate 36, so that distance data signals of object distance corresponding to the position of the focusing cam ring driven by the focusing mechanism 31 are input to the terminals DIS1, DIS2 and DIS3.

Terminal MACRO of the lens interface 41 is connected to the macro code portion 42 which functions as a macro switch which is turned ON when the zoom operation ring is actuated to switch the photographing lens 2 to the macro mode.

The input and output terminals of the lens interface 41 are connected to corresponding input and output terminals of the lens CPU 30. Reset terminal RESB, clock terminal CLK, serial-in terminal SIS, serial-out terminal SOS, terminal CE, terminal SOE, terminal ΦIN, and terminal KAFEND, of the lens interface 41 are connected to reset terminal RESET, serial clock terminal SCK, serial-out terminal SO, serial-in terminal SI, terminal P43, terminal P40, terminal PCL, and terminal POO of the lens CPU 30, respectively. Terminal CRES of the lens interface 41 is grounded through a delay capacitor C1.

The lens CPU 30 controls the PZ driver 33 connected to the control terminal thereof. The lens CPU 30 is also connected to the PZ pulser 35 and the lens judgement code 39.

Terminals P30, P31, P32 and P33 and terminals P62 and P63, of the lens CPU 30 are connected to the codes of the zoom code plate 37. The lens CPU 30 performs arithmetic operations based upon the input levels of terminals P30, P31, P32, P33, P62, and P63 in combination so as to obtain the focal length data at the zooming and at the macro mode.

The terminals P50, P51 and P52 and terminals P60 and P61, of the lens CPU 30 are connected to the K value telephoto extremity data setting portion 40. The lens CPU 30 calculates the K value data corresponding to the focal length and the object distance in accordance with the data formed by a combination of the levels of the terminals P50 through P53 and P60 and P61, using the K value at the telephoto extremity and at the infinite distance in the single focus macro mode.

Furthermore, terminals P21 through P29 of the lens CPU 30 are connected to various switches, such as the automatic focusing switch SWAF and the power zoom switches SWPZ1 and SWPZ2, etc., so that the lens CPU 30 performs a predetermined operation in response to the operations of the switches.

The photographing lens 2 has a clock pulse generating circuit 43 as a clock signal generating means which is connected to clock terminals X1 and X2 of the lens CPU 30. The lens CPU 30 operates synchronously with the clock pulses generated by the clock pulse generating circuit 43. The clock pulse generating circuit 43 comprises a timing control means.

As mentioned above, on the camera body side, after terminal CONT drops to level "L" and the open F-number is read, both the terminals CONT and RES (Fmin3) become level "H" to reset the lens CPU 30.

When the reset is released, the lens CPU 30 calculates specific data which is then set in the shift register in the lens interface 41 asynchronously with the clock pulses output from the camera body 1. The calculated data is successively outputted from the shift register in accordance with the clock signals of the camera body 1. This communication is carried out by hardware of the lens interface 41. In the illustrated embodiment, specific arithmetical data for 19 bytes is sent to the camera body 1.

Upon completion of the communication, terminal KAFEND of the lens interface 41 becomes level "L" which is a communication completion signal. Consequently, the lens CPU 30 waits for renewal data of the communication from the camera body 1.

When the lens CPU 30 receives the renewal communication data from the camera body 1, terminal DATA (Fmin2), which has been at level "H" becomes a level "L" and then becomes level "H" again, so that the camera body can commence the new communication. Note that the states of terminals CONT and RES when the lens CPU 30 is first activated are held.

In the new data communication, data is transferred from the photographing lens 2 to the camera body 1 or from the camera body 1 to the photographing lens 2, in accordance with the command code outputted from the camera body 1. The new data communication is effected synchronously with the clock pulse output from the photographing lens 2.

The data communicating between the photographing lens 2 and the camera body 1 is as shown in Tables 4 and 5 below.

                  TABLE 4                                                          ______________________________________                                         lens → body                                                             AF information        0011.0001(31H)                                           AE information        0011.0010(32H)                                           all data              0011.0011(33H)                                           each single bite      0101.XXXX(5XH)                                           lens information 1    0110.0000(60H)                                           lens information 2    0110.0001(61H)                                           body → lens                                                             focal length information fWide                                                                       0110.0010(62H)                                           focal length information fTele                                                                       0110.0011(63H)                                           focal length information fX(present)                                                                 0110.0100(64H)                                           lens drive information                                                                               0110.0110(66H)                                           lens accommodation    1001.0000(90H)                                           lens return           1001.0001(91H)                                           PH ON                 1001.0010(92H)                                           PH OFF                1001.0011(93H)                                           ______________________________________                                    

                  TABLE 5                                                          ______________________________________                                         lens info. 1     lens info. 2                                                                               lens drive                                        60 H             61 H        info. 66 H                                        ______________________________________                                         Bit 7   PH demand    LENS CPU    fw end                                        Bit 6   AF A/M                   fT end                                        Bit 5   PZ A/M       PZ in LENS                                                Bit 4   PZ P/A                                                                 Bit 3   PZ MODE                  PZ Far                                        Bit 2   SET SW                   PZ Near                                       Bit 1   LENS A/M     LENS                                                      Bit 0   LENS O/C     version                                                   ______________________________________                                    

Interface Circuit

The construction of the lens interface 41 will be described below in detail with reference to FIG. 4.

The lens interface 41 functions not only as input and output means for sending lens data of the photographing lens 2 to the camera body 1 in accordance with the sequential hardware control by the digital circuit, but also as an interface circuit for direct data communication by software between the indication CPU 11 of the camera body 1 and the lens CPU 30 of the photographing lens 2.

When the photographing lens 2 is attached to the camera body 1, so that the lock switch SWL is turned ON, a constant voltage is supplied from the camera body 1 (the terminal P16 of indication CPU 11) to the lens interface 41 through terminal CONT. Consequently, the reference constant voltage is supplied to terminal VDD of the lens CPU 30 from the terminal VDDB of lens interface 41. As a result, the lens CPU 30 activates the clock pulse generating circuit 43 by the reference constant voltage, so that the lens CPU 30 operates synchronously with the generated clock pulses. The lens interface 41 includes an I/O block 50 having the terminals VDDB, RES, etc., mentioned above.

The distance code plate 36 and the macro code portion 42 are connected to a pull-up buffer circuit 51, which pulls up the terminal level of the distance code plate 36 and the macro code portion 42 to send the output to an initial value setting register 52 in parallel as a part of an initial data of 3 bytes.

A pair of inputs of a NAND gate 51a, which is connected at the output thereof to the pull-up buffer circuit 51, are connected to terminals RES and CE. At a initial stage prior to the communication (previous communication). RES and CE are held at levels "L" and "H" by the indication CPU 11 and the lens CPU 30, respectively. Accordingly, the level of the output of the NAND gate 51a is "H", and the pull-up buffer circuit 51 fetches the initial data.

An internal initial value setting portion 53 and an external initial value setting portion 54 are connected to the input terminals of the initial value setting register 52. The initial value setting register 52 stores the initial data (unit of 1 byte) for three bytes outputted from the pull-up buffer circuit 51, an internal initial value setting portion 53 and an external initial value setting portion 54.

A group of output terminals of the initial value setting register 52 are connected to a group of input terminals of a data loading circuit 55 through a bus. The data loading circuit 55 functions to load the initial data for three bytes onto a 24 bit shift register 56 at one time and to load an arithmetic data group (discussed below) having a unit of 1 byte, onto a predetermined loading point LP of the 24 bit shift register 56. The 24 bit shift register 56 is of a parallel input and series output type which is schematically shown in FIG. 8.

The 24 bit shift register 56 performs the shifting in accordance with the clock pulses outputted from the indication CPU 11, so as to successively transfer the data latched in each flip-flop FF to terminal SOUT, from which the transferred data is serially output.

A series input and parallel output type of 8 bit buffer 57 is connected to the input of the data loading circuit 55. The arithmetic data operated in the lens CPU 30 is serially inputted into the 8 bit buffer 57 from input terminal SIS that is synchronously interfaced with the clock pulses outputted from the lens CPU 30.

The terminals CLK (clock) and CL (clear) of the 8 bit buffer 57 are connected to terminal CLK and terminal RES, respectively, of the I/O block 50. Output terminals Q0 through Q7 of the 8 bit buffer 57 are connected to terminals PR (FIG. 9) corresponding to flip-flop FF of the 24th stage of the 24 bit shift register 56 through a predetermined logic gate group, to be discussed hereinafter.

When the data for 8 bits is collected in the 8 bit buffer 57, the data is loaded on a predetermined portion after the loading points LP4, LP3, LP2, LP2, and LP0 of the 24 bit shift register 56 at a predetermined timing through the data loading circuit 55. The first arithmetic data for 8 bits is loaded on a portion immediately after the initial data for three bytes. Thereafter, the data is successively and continuously loaded immediately after the previously loaded arithmetic data.

The position of the flip-flop FF which latches the final bit of the data loaded in the 24 bit shift register 56 is detected by the counted values of an UP/DOWN counter 58. A load pointing decoder 59 sets the first flip-flop (i.e. the loading point LP) of 24 bit shift register 56 that loads the arithmetic data for one byte stored in the 8 bit buffer 57 (according to the counted values of the UP/DOWN counter 58). For example, when the initial data (or the arithmetic data) is shifted to the 9th flip-flop in FIG. 8, the arithmetic data of one byte is loaded in parallel on the flip-flops FF1 through FF8 after the loading point LP4.

The loading pulse generating decoder 60 connected to the UP/DOWN counter 58 through a bus generates control pulses to control the timing of the loading in accordance with the counted value of the UP/DOWN counter 58. For instance, every time the final data bit latched by the 24 bit shift register 56 reaches the loading points LP0 through LP4, the load pulse ("H" pulse) is outputted to a load pulse generating circuit 61.

The load pulse generating circuit 61, which receives the load pulse from the load pulse generating decoder 60 and a full signal from an 8 bit buffer full signal generating circuit 62, outputs the load pulse to the data loading circuit 55 through an OR gate 63. The data loading circuit 55 which receives the load pulse loads the arithmetic data latched by the 8 bit buffer 57 on a portion immediately after the loading point designated by the load pointing decoder 59.

When the load pulse is outputted from the load pulse generating circuit 61, the UP/DOWN counter 58 decreases the counted value by 8 bits for every output. As a result, the counted value of the UP/DOWN counter 58 is identical to the number of the flip-flop FF which latches the final data bit of the data loaded in the 24 bit shift register 56.

The output of the load pulse generating circuit 61 is connected to one of the input terminals of the OR gate 63. The other input terminal of the OR gate 63 is connected to the reset terminal RES of the I/O block 50 through an inverter 63a. The level of the reset terminal RES is "L" before the operation starts, and is held "H" during the old communication. Consequently, when load pulses of level "H" are outputted from the load pulse generating circuit 61 after the commencement of the communication, load pulses of level H are output from the OR gate 63 for every load pulse, so that the data loading circuit 55 performs the loading operation.

The 8 bit buffer full signal generating circuit 62 generates full signals in response to carrying signals output from an output terminal CARRY of an octal counter 71, which counts up every time the clock pulses outputted from the lens CPU 30 are sent to the serial clock input terminal CLK and outputs the carrying signals from the terminal CARRY every time an increase of a figure by one place takes place, respectively. The lens CPU 30 serially outputs the arithmetic data to the terminal SIS of the 8 bit buffer 57, synchronously with the serial clock signals.

The output of the OR gate 63 is also connected to the clear terminal CL of the 8 bit buffer full signal generating circuit 62 through the inverter 63b, so that when the level of the clear terminal CL is L, the 8 bit buffer full signal generating circuit 62 is cleared and the output is returned to the initial value.

An initial value/8 bit buffer switching circuit 64 switches the loading of the initial value into the 24 bit shift register 56 or the arithmetic data operated by the lens CPU 30 and latched by the 8 bit buffer 57. The output terminals Q and Q of the initial value/8 bit buffer switching circuit 64 are connected to the data loading circuit 55. Input terminal CL of the initial value/8 bit buffer switching circuit 64 is connected to terminal RES, and a clock terminal of the initial value/8 bit buffer switching circuit 64 is connected to the terminal SCK of the up/down counter 58 through an inverter 64a. Also, terminal D of the initial value/8 bit buffer switching circuit 64 is supplied with the reference voltage (level "H").

The level of the terminal RES of initial value/8 bit buffer switching circuit 64 is "L" at the initial state; the levels of terminals Q and Q are "L" and "H", respectively. In this state, initial data is loaded on the 24 bit shift register 56.

After that, the level of terminal RES becomes "H", so that when the clock pulse from the indication CPU 11 rises, the levels of terminals Q and Q are inverted and latched. As a result, the data of the 8 bit buffer 57 can be loaded on the 24 bit shift register 56.

Serial clock signals are inputted to the 24 bit shift register from the lens CPU 30 through a first SCL cancellation circuit 65, which cancels a first clock pulse after the commencement of the communication; and inputs a second clock pulse and clock pulses subsequent thereto into the 24 bit shift register 56. The 24 bit shift register 56 performs the shift operation in accordance with the serial clock signals.

A rear converter signal generating circuit 66 generates rear converter signals LR (level "L") to transfer data from a rear converter (not shown) to the indication CPU 11, in accordance with the counted value of the UP/DOWN counter 58, when the transfer of the initial data of three bytes and the arithmetic data of 13 bytes is finished. The 24 bit shift register 56 is disconnected from the indication CPU 11 in accordance with the rear converter signals LR.

The rear converter signal generating circuit 66 is connected to the output of the 8 bit buffer full signal generating circuit 62. Usually, signals LR are generated when the 24 bit shift register 57 is empty. To prevent the rear converter signals LR from being generated when the buffer is full at the loading point LPO, the output of the 8 bit buffer full signal generating circuit 62 is inputted to the rear converter signal generating circuit 66, as mentioned above.

An old communication completion signal generating circuit 67 outputs an old communication completion signal KAFEND (level "L") to the input terminal KAFEND of the I/O block 50 to complete the old communication when the counted value of the UP/DOWN counter 58 reaches a value which represents the completion of the transfer of the data for 19 bytes. Consequently, the lens CPU 30 completes the old communication in accordance with the KAFEND signal.

A reset circuit 68 resets the lens CPU 30 and has a terminal RES, to which a reset pulse is inputted from the indication CPU 11 through an inverter (not numbered), and an input terminal DATA, to which a discrimination pulse is inputted from the indication CPU 11, to discriminate a new lens. An input terminal STOP of the reset circuit 68 is connected to a output terminal Q of a stop signal (STOP) generating circuit 69, so as to place the lens CPU 30 into a sleep mode.

An output terminal RESB of the reset circuit 68 is connected to terminal RESET of the lens CPU 30 through terminal RESB. Output signal CRES of the reset circuit 68 is grounded through capacitor C1. Thus, the time in which the level of the CRES output signal drops from "H" to "L" is delayed.

The stop signal generating circuit 69 actuates the reset circuit 68 to place the lens CPU 30 into the sleep mode. Input terminal D and a clock input terminal of the stop signal generating circuit 69 are connected to output terminal Q1 of the 8 bit buffer 57 and the terminal CE of the I/O block 50, respectively. An output terminal Q of stop signal generating circuit 69 is connected to terminal STOP of the reset circuit 68.

Serial clock signal (SCK) switching circuit 70 selects the clock signals outputted from terminal CLK between those outputted from the indication CPU 11 of the camera body 1 and those outputted from the lens CPU 11. When the photographing lens 2 is mounted to the camera body 1, the SCK switching circuit 70 sends the serial clock signals from the lens CPU 30 to the terminal CLK during the old communication, and to the indication CPU 11 during the new communication, respectively.

Clear input signals and clock input of the SCK switching circuit 70 are connected to terminals RES and CE of the I/O block 50, respectively. An input terminal D of the SCK switching circuit 70 is connected to terminal Q0 of the 8 bit buffer 57. Terminals Q and Q of the SCK switching circuit 70 are connected to terminals SCKOUT and SCKIN of the I/O block 50, respectively.

The level of terminal Q of the SCK switching circuit 70 is "H" during the old communication, and is inverted to "L" if the level of terminal CE rises when the terminal Q0 of 8 bit buffer 57 is "H", upon completion of the old communication. Due to the inversion, the clock signals are switched as mentioned above.

The serial clock is inputted from terminal CLK to the input CLK of the octal counter 71 which counts the clock signals from the lens CPU 30 during the old communication. Octal counter 71 outputs the carrying signals from terminal CARRY thereof every time 8 pulses are counted. Since input terminal CL of the counter 71 is connected to terminal RES, the level of the input terminal CL rises to "H" upon transfer to the old communication from the initial state.

Decoder 72 receives the counted value of the counter 71 to decode the data bits fetched by a code plate data selection circuit 73. The code plate data selection circuit 73 selects the data of the distance code plate 36, or the macro code portion 42, through the pull-up buffer circuit 51, synchronously with the decoding operation and outputs the selected data from terminal DATA. The output data is received in the lens CPU 30.

The above discussion has been directed to the construction and operation of the lens interface 41.

I/O Block

The following description will be directed to the construction of the I/O block 50, with reference to FIG. 5.

The I/O block 50 has terminal RES connected to terminal P12 of the indication CPU 11 of the camera body 1, terminal SCK connected to terminal P10, and terminal DATA connected to terminal P11. Terminal RES is also connected to terminal RES through an inverter 75. An emitter of a transistor Tr3 is connected to a line between terminal RES and the inverter 75. A base of the transistor Tr3 is connected to terminal SLCT3, and a collector of the transistor Tr3 is grounded. The reset signal is sent to terminal RES from the indication CPU 11.

Terminal SCK is connected to one of the inputs of an AND gate 77, an input of a tristate buffer 78, and an output of a tristate buffer 79. The output of the AND gate 77 is connected to output SCK. The output of the tristate buffer 78 and the input of the tristate buffer 79 are connected to terminal CLK and output CLK. The other input of the AND gate 77 is connected to the input KAFEND.

The emitter and the base of the transistor Tr1 is connected to a line between the terminal SCK which the base of the transistor TR1 is connected to inverter 76, and the terminal SLCT1. The collector of the transistor Tr1 is grounded.

The DATA terminal is connected to an output of a tristate buffer 80, one of a pair of inputs of a multiplexer 81, and the output DATA. The output of the multiplexer 81 is connected to terminal SOS.

The clock terminal CLK, terminal SOS, terminal SIS, terminal CE and terminal SOC, which are connected to the lens CPU 30, will be described below.

The CLK terminal is connected to the output CLK, the output of the tristate buffer 78, and the input of the tristate buffer 79. The CLK terminal transmits and receives clock pulses to and from the SCK terminal of the lens CPU 30. The CLK output receives the serial clock signal from the indication CPU 11 or from the lens CPU 30.

The tristate buffers 78 and 79, having opposite directions, are connected in parallel between a portion between the CLK terminal and the CLK output and a portion between the SCK terminal and the inverter 76. Consequently, the connection and disconnection between the SCK terminal and the CLK output and between the CLK terminal and the SCK terminal can be selectively controlled by the control of the tristate buffers 78 and 79.

The control input of the tristate buffer 79 is connected to the output of AND gate 83. One of a pair of inputs of the AND gate 83 is connected to the output of AND gate 84, and the other input thereof is connected to terminal SCKOUT. The inputs of the AND gate 84 are connected to terminal KAFEND through the inverter 86 and to terminal CE, respectively.

Terminal SOS is connected to the output of the multiplexer 81. The data inputs of the multiplexer 81 are connected to terminal DATA and terminal CODE, respectively. Accordingly, data from the indication CPU 11, the macro code plate 42 and the distance code plate 36 is selectively outputted.

The control inputs of the multiplexer 81 are connected to terminal CE and output terminal CE through the inverter 90, respectively. Consequently, the switching of the input of the multiplexer 81 is controlled by the level of terminal CE. Namely, when the level of terminal CE is "L", the data of the input CODE is output to terminal SOS, and when the level of terminal CE is "H", the data of terminal DATA is outputted from terminal SOS.

The data outputted from terminal SO of the lens CPU 30 is input to terminal SIS. Terminal SIS is connected to output SIS and the other data input of the multiplexer 87. Accordingly, terminal SIS is selectively connected to terminal DATA between terminal DATA and input SOUT by the multiplexer 87. Output SIS is connected to input SIS of the 8 bit buffer 57. Consequently, the data outputted from terminal SO of the lens CPU 30 is sent directly to terminal DATA and to terminal DATA through the 24 bit shift register 56.

Terminal CE is connected not only to one control input of the multiplexor 81, and the other control input of the multiplexer 81 through the inverter 90, but also to the second input of the AND gate 84. Consequently, the terminal CE functions as a selection terminal to select data from the photographing lens 2 to the camera body 1 from among the data of the macro code plate 42 and the distance code plate 36, the data through the 24 bit shift register 56, and the data output from the lens CPU 30.

Terminal SOE is connected to the input of the OR gate 88 through the inverter 82. Terminal SOE functions as a control terminal to control the output of the tristate buffer 80 during communications other than the old communication.

The levels of the various terminals which function in the initial state, the old communication state and the new communication state will be described below.

In the initial state, the levels of the reset terminal RES and the serial clock terminal SCK are maintained "H", by the indication CPU 11 (see as shown in the state before time a in FIG. 10). In this state, initial data of the distance code plate 36 and the macro code portion 42, etc., are loaded in the 24 bit shift register 56.

At an commencement of a "L" level old communication, the reset pulse is outputted from the reset terminal RES. The lens CPU 30 performs an initialization in response to the reset pulse. At that moment, the initial value set in the initial value setting register 52 is loaded in the 24 bit shift register 56 (as shown at time a in FIG. 10).

Thereafter, the levels of terminal CE and terminal SOE become "L", the clock pulse from the lens CPU 30 is outputted to terminal CLK, and the clock pulse from the indication CPU 11 is outputted to output SCK. During the old communication, the levels of input, KAFEND, input LR and terminal SCKOUT are "H". In this state, the data outputted to input SOUT is output from terminal DATA.

Upon completion of the transfer of 16 bytes, of data the level of input LR is "L", so that the connection of input SOUT and terminal DATA is broken. During the disconnection, if the rear converter is mounted, data from the rear converter is outputted to the indication CPU 11.

After the time for 19 bytes of data transfer lapses, the level of the input KAFEND becomes "L", and the clock pulses outputted from the camera body to output SCK are interrupted.

Reset Circuit

The arrangement of the reset circuit 68 will be described below in more detail with reference to FIGS. 6 and 7.

Input RES and input DATA of the reset circuit 68 are connected to terminal RES and terminal DATA of the I/O block 50, respectively. Input STOP of the reset circuit 68 is connected to output Q of the stop signal generating circuit 69. Output RESB of the reset circuit 68 is connected to terminal RESET of the lens CPU 30, and output CRES is grounded through the delay capacitor C1.

Input RES is also connected to terminal CRES through one of a pair of inputs of NAND gate 91 and a pull-down resistor R1. The output of the NAND gate 91 is connected to the gate of a MOS field effect transistor FET1, a drain of which is connected to a line between the resistor R1 and output CRES. The source of the field effect transistor FET1 is grounded. The line between the resistor R1 and the output CRES is connected to the output terminal RESB through a Schmidt inverter 93 and an inverter 94 that is connected in series thereto.

Input terminal DATA and input terminal STOP are connected to respective inputs of OR gate 96, with the stop input first being inverted by inverter 95. The output of the OR gate 96 is connected to a second input of the NAND gate 91.

The timing chart of the reset circuit 68 will be explained below (see FIG. 7). At the initial state, the levels of terminal RES and terminal DATA are both "H", and the levels of input terminal RES, input STOP and output RESB are all "L".

When the level of terminal RES (terminal Fmin3) is made "L" by the indication CPU 11, output RES is inverted by the inverter 75 and becomes level "H". As a result, the level of input CRES becomes "H", and the level of output RESB is made "H" through the Schmidt inverter 93 and the inverter 94.

In this state, even if the level of input DATA falls, the level of the OR gate 96 is maintained at "H", and the level of the NAND gate 91 is maintained at "L", so that the field effect transistor FET1 is maintained OFF. Consequently, the level of output RESB is held to be "H".

If input DATA falls to "L" when input STOP (the output Q of the stop signal generating circuit 69) is "H", the levels of the OR gate 96 and the NAND gate 91 change from "L" to "H", so that the field effect transistor FET1 is turned ON. Accordingly, the level of output RESB is changed to "L". As a result, the lens CPU 30 is reset.

24 Bit Shift Register

The following discussion will be addressed to the construction and loading operation of the data loading circuit 55 and the 24 bit shift register 56, with reference to FIGS. 8 and 9 and Table 6. The flip-flops FF1 through FF8 in FIG. 9 are flip-flops of the first eight bits corresponding to No.1 through No.8 flip-flops in FIG. 8.

                                      TABLE 6                                      __________________________________________________________________________                       The data to be loades to 24 bit flip-flop                    INPUT             "--" indicates the data not to be loaded                     Q   Q RES                                                                               LD LP3                                                                               LP4                                                                               1   2   3   4   5   6   7   8   REMARKS                      __________________________________________________________________________     a 0 1 0  0  0  0  INIT                                                                               INIT                                                                               INIT                                                                               INIT                                                                               INIT                                                                               INIT                                                                               INIT                                                                               INIT                                                                               The initial value is                                                           loaded                                         23  22  21  20  19  18  17  16                               b 0 1 1  0  0  0  --  --  --  --  --  --  --  --  Not loaded                   c 1 0 1  0  0  0  --  --  --  --  --  --  --  --                               d 1 0 1  0  0  1  --  --  --  --  --  --  --  --                               e 1 0 1  0  1  0  --  --  --  --  --  --  --  --                               f 1 0 1  1  0  0  --  --  --  --  Q0  Q1  Q2  Q3  The calculated data is                                                         loaded to LP3                g 1 0 1  0  0  0  --  --  --  --  --  --  --  --  Not loaded                   h 1 0 1  0  0  1  --  --  --  --  --  --  --  --                               i 1 0 1  0  0  1  Q0  Q1  Q2  Q3  Q4  Q5  Q6  Q7  The calculated data is                                                         loaded to LP4                j 1 0 1  0  0  0  --  --  --  --  --  --  --  --  Not loaded                   : 1 0 1  :  :  :  :   :   :   :   :   :   :   :                                n 1 0 1  1  0  0  --  --  --  --  --  --  --  --  The calculated data is                                                         loaded to either LP0,                                                          LP1                                                                            or LP2.                      : 1 0 1  :  :  :  :   :   :   :   :   :   :   :                                __________________________________________________________________________

The load point pulses ("H" level) are selectively outputted to terminals LP3 and LP4 when the data of the 8 bit buffer 57 is loaded on the load point LP3 or LP4 of the 24 bit shift register 56 from the load point decoder 59.

Upon loading, the load pulse (level "H") is outputted to terminal LD from the load pulse generating circuit 61 through the OR gate 63.

The reset pulse is inputted to terminal RES from the indication CPU 11 through terminal RES of the I/O block 50.

The serial clock pulse is inputted to terminal SCK1 from terminal SCK of the I/O block 50 through the first clock pulse cancellation circuit 65.

Terminals Q and Q are connected to the outputs Q and Q of the initial value/8 bit buffer switching circuit 64, respectively.

Input D of the first flip-flop FF1 is grounded, and the inputs of the 2nd through 8th flip-flops FF2 through FF8 are connected to outputs Q of the preceding flip-flops FF1 through FF7, respectively. The initial value of output Q is level "L", since input D of the first flip-flop FF1 is grounded.

The data pulses are input to inputs PR (preset inputs) of the flip-flops FF1 through FF8 from the data loading circuit 55, and the clear pulse is input to inputs CL (clear inputs) to latch the data (level) of the inputs PR (preset inputs).

The flip-flops FF1 through FF8 perform the shift operations when the clock pulse input from the terminal SCK1 rises.

The surroundings of the flip-flops FF2 through FF4 are similar to those of the first flip-flop FF1, and the surroundings of the flip-flops FF5 through FF8 are similar to those of the fifth flip-flop FF5. Accordingly, only the surroundings of the first and fifth flip-flops FF1 and FF5 are described below.

The bit data of a unit of one byte is inputted into inputs PR (reset inputs) of the flip-flops FF from the corresponding outputs Q0 through Q7 through a logical gate group. The data of the initial value setting register 52 and the outputs Q0 through Q7 of the 8 bit buffer 57 are inputted to the preset inputs of the flip-flops FF1 through FF8 through the logical gates, respectively.

One of the inputs of AND gate 101A of the first stage is connected to terminal Q and the other input is connected to terminal INIT23, which is an output terminal of the initial value setting register. Consequently, the AND gate 101A outputs the initial value data of terminal INIT 23 to the flip-flop FF1.

Three inputs of AND gate 101B of the first stage are connected to terminal LP4, terminal Q0 and terminal Q. Consequently, the AND gate 101B outputs the data of terminal Q0 to the flip-flop FF1.

One of the inputs of AND gate 105A of the fifth stage is connected to terminal Q, and the other input is connected to the terminal INIT19 which is a data output terminal of the initial value setting register 52. Consequently, AND gate 105A outputs the initial value data of terminal INIT 19 to the flip-flop FF5.

Three inputs of AND gate 105B of the fifth stage are connected to terminal LP4, terminal Q4 and terminal Q. Consequently, AND gate 105B outputs the data of terminal Q4 to the flip-flop FF5.

Three inputs of AND gate 105C are connected to terminal LP3, the terminal Q0 and the terminal Q. Consequently, AND gate 105C outputs the data of terminal Q0 to the flip-flop FF5.

As can be seen from the above discussion, AND gates 101A and 105A load the initial value data on the flip-flops FF1 and FF5. Similarly, AND gate 101B loads the data of Q0 on the flip-flop FF1, and AND gates 105B and 105C load the data of Q4 and Q0 on the flip-flop FF5, respectively.

Thus, the reset circuit loads the initial value data of 24 bits on the corresponding flip-flops and loads the data of Q0 through Q8 of the 8 bit buffer 57 on positions shifted in the right hand direction by 4 bits, respectively.

The outputs of the AND gates 101A and 101B are connected to the inputs of OR gate 111, respectively. Accordingly, when one of the outputs of the AND gates 101A and 101B becomes "H", the level of the output of the corresponding OR gate 111 becomes "H".

The outputs of the AND gates 105A, 105B and 105C are connected to respective inputs of the OR gate 115. Accordingly, when one of the outputs of the AND gates 105A, 105B and 105C becomes "H", the level of the output of the OR gate "115" becomes H.

The output of the OR gate 111 is connected to one of the inputs of NAND gate 121, and one of the inputs of NAND gate 141 (via inverter 131). The other inputs of the NAND gates 121 and 141 are connected to the output of OR gate 152. The output of NAND gate 121 is connected to preset input PR of flip flop FF1 and the output of the NAND gate 141 is connected to input CL of flip flop FF1.

Similarly, the output of the OR gate 115 is connected to one of the inputs of NAND gate 125, and one of the inputs of the NAND gate 145 (via inverter 135). The other inputs of the NAND gates 125 and 145 are connected to the output of OR gate 156. The outputs of the NAND gates 125 and 145 are inputted to present input PR and the input CL of flip-flop FF5, respectively.

Consequently, when the level of the output of the OR gate 152 is "H" and the level of the output of the OR gate 111 is "H", the level of the output of the NAND gate 121 is "L" and data of level "H" is loaded in the flip-flop FF1.

Furthermore, when the level of the output of the OR gate 152 is "H" and the level of the output of the OR gate 111 is "L", the level of the output of the NAND gate 141 is "L" and data of the terminal INIT 23 is loaded in the flip-flop FF1.

Conversely, when the level of the output of the OR gate 156 is "H" and the level of the output of the OR gate 115 is "H", the level of the output of the NAND gate 125 is "L" and data of level "H" is loaded in the flip-flop FF5.

Furthermore, when the level of the output of the OR gate 156 is "H" and the level of the output of the OR gate 115 is "L", the level of the output of the NAND gate 145 is "L" and data of the INIT 19 is loaded in the flip-flop FF5.

Terminal LP3 is connected to one of the inputs of the AND gate 105C and one of the inputs of the OR gate 154. The other input of the OR gate 154 is connected to terminal LP4. Accordingly, when one of the terminals LP3 and LP4 is "H", the output of the OR gate 154 is "H".

The output of the OR gate 154 is connected to one input of AND gate 155. The other input of the AND gate 155 is connected to terminal LD. Consequently, the level of the output of the AND gate 155 becomes "H" and "L" when the level of one of the outputs of terminal LP3 or LP4 is "H" and when the level of terminal LD is "H", respectively.

The output of the AND gate 155 is connected to one of the inputs of the OR gate 156. The other input of the OR gate 156 is connected to terminal RES through the inverter 153. The output of the OR gate 156 is connected to one of the inputs of the NAND gates 125 and 145, as mentioned above.

Terminal LP4 is connected to one of the inputs of the AND gate 151, one of the inputs of the OR gate 154, one of the inputs of the AND gate 105B and one of the inputs of the AND gate 101B.

Terminal LD is connected to the other input of the AND gate 151 and AND gate 155.

The terminal RES is connected to one input of OR gates 152 and 156, through inverter 153.

Terminal SCK' is a clock terminal which is connected to the clock inputs of the flip-flops FF1 through FF8 in order to perform the shift operation.

Terminals Q and Q are connected to one of the inputs of the AND gates 101A and 105A and to one of the inputs of the AND gates 101B, 105B and 105C, to selectively load or initialize the data, respectively.

Loading of Data in course of Old Communication

The loading operation of the data by the loading circuit shown in FIG. 9 in the course of the old communication will be described below with reference to FIG. 10, which shows a timing chart of the loading operation.

Since the levels of terminals RES, SCK, and Q are "H" at the initial stage, the initial data of the terminals INIT23˜INIT16 are loaded on the flip-flops FF1˜FF8.

When the level of terminal RES falls to "L" and when the level of terminal RES rises to "H", the loading of the initial data is completed (time a).

Thereafter, the serial clock signal from the camera body 1 is outputted from terminal SCK. The UP/DOWN counter 58 begins counting the SCK clock pulses.

The first SCK cancellation circuit 65 cancels the first clock pulse of the input SCK clock pulses and outputs the clock pulses subsequent to the first clock pulse as SCK1 clock pulses to the 24 bit shift register 56. The flip-flops FF begin the shifting operation in accordance with the SCK1 clock pulses.

As a result, the level of the RES clock pulse inputted to input CL of the initial value/8 bit buffer switching circuit 64 becomes "H". Accordingly, the SCK clock pulse rises. Consequently, outputs Q and Q are inverted, so that the levels of the outputs Q and Q become "H" and "L", respectively. Thus, the data of Q0˜Q7 of the 8 bit buffer 57 can be loaded (time b).

When the seven SCK1 pulses are inputted to the flip-flops FF, the flip-flops FF1 through FF8 are vacant. When the counted value of the UP/DOWN counter 58 is seven, the load pulse generating decoder 59 rises the LP4 pulse to hold it at level "H" in accordance with the falling of the eighth SCK clock pulse. In this state, when the carrying signal is outputted from the octal counter 71, the LD load pulse of level "H" is outputted through the load pulse generating circuit 61, so that data of Q0˜Q7 of the 8 bit buffer 57 are loaded in the flip-flops FF1˜FF8, respectively.

In the illustrated embodiment, since the 8 bit buffer 57 is not full in this state, no carrying signal is outputted from the octal counter 71, so that no data of the 8 bit buffer 57 is loaded.

The output of the SCK clock pulse continues and the initial data is shifted. When the twelfth SCK clock pulse falls, load pointing decoder 59 causes LP4 and LP3 pulses to fall and rise (time d), respectively. As a result, the data of Q0˜Q3 can be loaded in the flip-flops FF5˜FF8. Note that data Q4˜Q7 is able to be loaded in the flip-flops preceding the flip-flop FF8.

When the 8 bit buffer 57 is full, so that the carrying pulse is outputted from the octal counter 71, the load pulse is outputted from the load pulse generating decoder 60. Accordingly, the LD load pulse rises. As a result, data Q0˜Q3 are loaded in the flip-flops FF5˜FF8 (time e). Consequently, a decrement of the counted value of the UP/DOWN counter 58 by 8 takes place, so that the value is changed to 5 from 13.

When four SCK clock pulses are outputted and the counted value of the UP/DOWN counter 58 changes from 7 to 8, the LP4 pulse rises in accordance with the fall of the SCK clock pulse, so that the data can be loaded at load point LP4 (time h).

The output of the LD pulse causes the carrying pulse to be generated from the octal counter 71 to load the data of Q0˜Q7 in the flip-flops FF1˜FF8 (time i).

The hardware operations mentioned above are repeated to first load the initial data of 3 bytes on the 24 bit shift register 56, so that the data is serially outputted from the 24 bit shift register 56 while being shifted by 1 bit to be transferred to the camera body 1 (the indication CPU 11) through the terminal DATA.

During the loading and shifting of the initial data, the lens CPU 30 performs a predetermined arithmetic operation. When the arithmetic data of a unit of one byte is loaded from the 8 bit buffer 57 into the 24 bit shift register 56, so that the data is transferred to the camera body 1 from the 24 bit shift register 56, subsequent to the initial data.

Upon completion of the transfer of the initial data of 3 bytes and the arithmetic data of 13 bytes, the LR pulse of level "L" is outputted from the rear converter signal generating circuit 66, so as to break the connection between terminal SOUT and terminal DATA. If the rear converter is mounted, the data of 3 bytes of the rear converter is transferred to the camera body 1 synchronously with the clock signal of the lens CPU 30 after the connection is broken.

Upon transfer of the rear converter data of 3 bytes, the old communication completion KAFEND pulse of level "L" is outputted from the KAFEND signal generating circuit 67 to complete the old communication. Note that the lens CPU 30 does not operate until a time for transferring data for 19 bytes lapses, even if no rear converter is mounted.

When the KAFEND pulse is outputted as the old communication completion signal (the lens CPU 30 to which the received completion signal is ready for a new communication). When the lens CPU 30 receives an old and new communication switching command output from the indication CPU 11, the lens CPU 30 outputs the acknowledgement signal and performs another operation.

In the illustrated embodiment, although the initial value data which does not require the arithmetic operation is three bytes, it can be two bytes, four bytes or more. It is possible to use a shift register other than the 24 bit shift register 56, corresponding to or not corresponding to the initial value data. For instance, a 16 bit shift register or a 32 bit shift register can be used instead of the 24 bit shift register.

The basic operations of the camera system of the present invention will now be described below in detail.

Timer Routine of Indication CPU

First, the main operation (timer routine) of the indication CPU 11 will be explained with reference to FIG. 12. The main operation is performed by the indication CPU 11 in accordance with a program stored in an internal ROM 11a of the indication CPU 11.

The indication CPU 11 checks whether the lock switch SWL is turned ON or OFF at steps S11 and S12. If the lock switch SWL is turned OFF, interruption of the operation by the switch is prohibited (step S13). The state of the lock flag FLOCK is then checked to determine if the lens is in a retracted position (step S14).

Usually, in a photographing lens, the whole length of the lens is varied in accordance with the focusing and zooming operations. Therefore, when no picture is taken, it is preferable to reduce the whole length of the photographing lens to be as short as possible, in order to realize a compact and portable camera.

To this end, in the camera system of the present invention, the photographing lens 2 is automatically retracted to reduce the whole length thereof by the automatic focusing mechanism and the power zoom mechanism when the lock switch SWL is turned OFF.

However, a photographer makes the lock switch SWL OFF also when he or she does not intend to retract the photographing lens in the camera. For instance, the lock switch SWL may be turned OFF to reduce the power consumption when a photographer waits for the next shot, while maintaining the focal length and focal point as they are. In such a case, if the photographing lens is automatically retracted when the lock switch SWL is turned OFF, the focal length and focal point vary, so that the photographer must troublesomely readjust the focal length and focal point.

To prevent this, in the camera system according to the present invention, when the lock switch SWL is switched from ON to OFF, the focal length and the focal point at that time are memorized and then, the photographing lens is retracted. When the lock switch SWL is turned ON again, the focal length and the focal point before the retraction of the photographing lens are automatically obtained, regardless of the photographer's intention when the lock switch SWL is turned OFF. Thus, according to the present invention, the problem mentioned above can be eliminated.

In the camera system of the present invention, the retraction and return operations with respect to the automatic focusing mechanism are carried out by the main CPU 10, and the retraction (accommodation) and return operations with respect to the power zoom mechanism are carried out by the lens CPU 30, respectively. Note that the main CPU 10 and the lens CPU 30 are supplied with electrical power only when they operate. Otherwise no power is supplied thereto. Therefore, the data of the retraction and the return is controlled by the indication CPU 11 which always operates. The transmission of the data, not including the initial data, and the commands between the lens CPU 30 and the indication CPU 11 is affected by the new communication.

The lens retraction (accommodation) operation is affected at steps S15 through S18. Since the zooming operation is controlled by the lens CPU 30, code 90H for the accommodation command is sent to the lens CPU 30. The focal length data, before the accommodation, is inputted from the zoom code plate 37 to the lens CPU 30. The automatic focusing operation, which is controlled on the camera body side, is performed by the main CPU 10 in an AF accommodation sub-routine at step S17.

Upon completion of the accommodation operation, the lock flag FLOCK is removed (step S18), and control proceeds to step S19. If the lens has already been accommodated or retracted, since the lock flag FLOCK is set to 0, control skips step S15 through step S18.

At step S19, terminal P16 (terminal CONT) falls to "L" and then the power source to the lens CPU 30 and the LCD 12 are turned OFF (step s20). Thereafter, a timer routine is performed for a 125 ms cycle (steps S21 through S23). That is, the intermittent operation by the timer operation is repeated during the period in which the lock switch SWL is OFF.

If the lock switch SWL is turned ON during the operation at step S12, the indication CPU 11 determines the state of the lock flag FLOCK at step S24. If FLOCK is set to 0, the AF return operation is performed by the main CPU 10 to return the focal point of the photographing lens to one before the accommodation (retraction) operation.

At step S26, kind of the attached lens is determined in accordance with the input data. If necessary and if possible, the lens CPU 30 performs the return of the zoom mechanism.

Upon completion of the data input operation, interruption of control by the photometer switch SWS and the release switch SWR is permitted, so that the release can be effected. Thereafter, control proceeds to step S28.

When the mode switch SWM, the drive switch SWDR, the exposure correction switch SWXV and the up-down switch SWUP/DN are actuated, the changing operation of the mode, etc., and the indication operation of the selected mode are performed at steps S28 through S35.

If none of these switches is actuated, or if the switching operation is finished, an intermittent operation is performed in accordance with the timer operation at steps S21 through S23.

Input operation of Lens Data

The sub-routine for the input operation of the lens data which is called at step S26 of the timer routine will be described below with reference to FIGS. 11 and 13A-13C. The input operation is performed by the indication CPU 11.

First, three lens flags FAE, FCPU and FNO, for discriminating the lens, are reset to 0 (step S40). The lens flag F AE discriminates a conventional (old) AE lens having a lens ROM, the lens flag FCPU discriminates a new AE lens having a lens CPU, for example, the photographing lens 2 having the lens CPU 30 shown in FIGS. 1 and 3, etc., and the lens flag FNO discriminates a manual lens having no lens CPU, respectively.

After that, it is determined whether the lock flag FLOCK is set to 1 at step 41. If FLOCK is set to 0, control proceeds to step S42. Conversely, if FLOCK is set to 1, control jumps to step S53.

At step S42, terminals P10 through P12, which are used for serial communication with the photographing lens 2, are set to the input mode, and then, level of the terminal P16 (the contact Cont) is inputted and checked (steps S43 and S44).

If there is no contact Cont on the mounted lens side, contact Cont on the camera body side comes into contact with the surface of the lens mount and is accordingly grounded, measuring that the mounted lens is an old AE lens.

When the mounted lens is the old AE lens, the levels of terminals P10 through P15 are inputted to read the open F number and the minimum F number and the diaphragm A/M switching data, and the old AE lens flag FAE is made 1 (steps S45 and S46). Then, control is returned.

If no photographing lens is mounted, or if a lens having lens data is mounted, the level of the Cont contact is "H". Consequently, the level of terminal P16 falls to "L" to stop the supply of electrical power to the lens side. Thereafter, the levels of the other terminals P10 through P14 are inputted (step S48).

At this moment, all the levels of terminals P10 through P14 are checked to determine whether they are all "H". If the levels are all "H", then the no lens flag FNOL, which represents a normal lens having no CPU, is set to 1 (Steps S48-2 and S52). Thereafter, control is returned.

As can be seen in FIG. 3, when the transistors Tr are connected to the lens contacts Fmin1 through Fmin3, the open F number can be detected in accordance with the levels of the lens contacts Fmin1 through Fmin3 in combination, depending on the ON and OFF state of the transistors Tr in combination. The maximum F number can be detected in accordance with the levels of the lens contacts Fmax1 and Fmax2 in combination, depending on the ON and OFF state of the switches SWFmax1 and SWFmax2 in combination. The level of the diaphragm A/M contact is used to detect whether the diaphragm is automatic or manual.

Thereafter, the level of terminal P16 becomes "H" to supply the lens side with power, so as to activate the lens CPU. After that, levels of the terminals P10 through P14 are inputted (steps S49 and S50). Whether the levels of terminals P10 through P12 are all "H" is checked at step S51. If the levels of P10, P11 and P12 are all "H", the normal lens flag FNO, which represents a normal lens having no lens CPU, is set to "1" at step S52. Thereafter, control is returned.

If any of the levels of terminals P10, P11 and P12 is "L", it is determined whether both the levels of terminals P13 and P14 are "H" at step S53. If both the levels of both terminals P13 and P14 are "H", the normal lens flag FNO is set to 1 (step S52), since it is then considered that there is trouble with the lens CPU. Control is then returned.

If at least one of the terminals P13 or P14 is "L", the level of terminal P10 falls to "L" (step S54), and terminals P11 and P12 are set to the serial communication mode (step S55), since the mounted lens is a new AE lens (e.g. the photographing lens). Thereafter, control proceeds to step S56.

At step S56, the lock flag FLOCK is checked to determine if it is set to 1. If FLOCK is to 0, control proceeds to step S57, and if FLOCK is set to 1, control jumps to step S66.

At step S57, the lens data of 16 bytes and the rear converter data of three bytes are inputted by the old communication.

When the input of the data by the old communication is completed, the body CPU11 checks whether the lens connected to the body is a lens with a lens CPU 30 or it does not have a lens CPU. If not, which means that the lens is a common AE lens, flag FLROM is set to 1 (Steps S57-2 and S57-3). Thereafter, control is returned.

When the input of the data by the old communication is completed, the new/old communication switching signal is outputted from terminal DATA (step S58), so that the clock demand signal is outputted to the lens side in response to the acknowledgement signal issued from the lens side, whereby the lens CPU 30 outputs the clock signal (steps S59 and S60).

Thereafter, a lens return command code 91H is sent to the lens CPU 30, which is ready for returning the power zoom mechanism at step S61. Control waits until the acknowledgement signal is issued from the lens CPU 30 (step S62).

Upon receipt of the acknowledgement signal, the focal length data, before accommodation, is sent to the lens CPU 30, which then performs a power zooming operation (step S63). When the power zooming is finished, which can be detected by the issuance of the acknowledgement signal from the lens CPU 30, lock flag FLOCK is set to 1 (steps S64 and S65). Thereafter, control proceeds to step S66.

At step S66, a clock demand signal is outputted, so that the lens CPU 30 outputs the clock signal. The command code 60H is synchronously outputted with the clock signal, and the control does not proceed until the acknowledgement signal is issued (steps S67 and S68). The command code 60H is used to read lens information, including the switch setting data on the lens side and the power hold demand signal, etc.

Upon receipt of the acknowledgement signal, the lens information output from the lens CPU 30 is received (step S69). The completion of the receipt of the lens information is detected by the receipt of the acknowledgement signal fed from the lens CPU 30 (step S70).

Upon receipt of the acknowledgement signal, it is determined whether the transferred data demands a power hold (step S71). If there is a power hold demand, the lens CPU 30 is requested to output the clock signal (step S72). Thereafter, the level of terminal P18 becomes "H" and control does not proceed until the acknowledgement signal is issued from the lens CPU 30 (steps S73 and S74).

Upon receipt of the acknowledgement signal, a power hold-ON code 92H is outputted (step S75). Thereafter, control proceeds to step S81.

If there is no power hold demand at step S71, the output of the clock signal is demanded at step S76. Thereafter, a power hold-OFF code 93H is synchronously outputted with the clock signal (step S77). After that, it is determined whether the acknowledgement signal is output from the lens CPU 30 at step S78.

Upon receipt of the acknowledgement signal, the level of terminal P18 becomes "L" after a lapse of a predetermined period of time (steps S79 and S80) so as to stop the supply of power to the PZ motor 34. Then, control proceeds to step S81.

At step S81, the output of the clock signal is demanded. The demand code 61H for demanding the lens information 2 is synchronously outputted with the clock signal at step S82. Thereafter, it is determined whether the acknowledgement signal is output at step S83.

When the acknowledgement signal is received, the subsequent lens information 2 is received at step S84. Thereafter, it is determined whether the acknowledgement signal is output at step S85.

When the acknowledgement signal is received at step S85, the clock signal is demanded at step S86. A demand code 33H demands that all the data is synchronously outputted with the clock signal at step S87. Thereafter, it is determined whether the receipt acknowledgement signal is received is at step S88.

If the receipt acknowledgement signal is received, the subsequent data for 16 bytes is inputted at step S89. Thereafter, it is determined whether the transmission completion acknowledgement signal is received at step S90.

If the transmission completion acknowledgement signal is received at step S90, it is determined whether there is a power hold demand at step 91. If there is a power hold demand, the new AE lens flag FCPU is set to 1 (step S95), and then, control is returned.

Conversely, if there is no power hold demand at step S91, the clock signal is demanded at step S92 and a predetermined code is outputted (step S93). Thereafter, it is determined whether the receipt acknowledgement signal is received at step S94.

Main Routine of Lens CPU

The lens CPU 30 starts when the reset circuit 68 releases the reset after the levels of terminal Cont and contact Fmin1 are made "H" by the indication CPU 11.

The lens CPU 30 performs the initialization after the interruption by all of the operations is prohibited (steps S100 and S101 of FIG. 14).

After the initialization is completed, it is determined whether the old communication completion signal is outputted from the lens interface 41. That is, it is determined whether the level of terminal KAFEND is "L" at step S102. If the old communication completion signal is outputted stop flag FSTOP is set to 1, and then, a lens CPU interruption starts (step S103).

Conversely, if no old communication completion signal is outputted, which means that control is still during the old communication, the states of the switches are inputted and stored in the RAM to successively perform the predetermined arithmetic operations (step S105). During these operations, the initial value data is loaded into the 24 bit shift register 56, in which the data is shifted and serially outputted to the indication CPU 11.

Every time the predetermined arithmetic operations are finished, the results of the arithmetic operations (arithmetic data) are outputted to the lens interface 41 (step S106). The arithmetic data outputted to the lens interface 41 is then loaded into the 24 bit shift register 56 by hardware and successively transferred to the indication CPU 11 through the I/O block 50, as mentioned above.

If a rear converter is provided, data for 3 bytes is also transferred to the indication CPU 11 from the rear converter. When the transfer of the data for 19 bytes in total, including the initial data for 3 bytes, the arithmetic data for 16 bytes and the rear converter data for 3 bytes is completed, the lens interface 41 outputs the old communication completion signal.

Upon completion of the output of the arithmetic data to the indication CPU 11, it is determined whether the old communication completion signal is outputted at step S107.

When the old communication completion signal is received, the new/old communication switching signal is inputted from the indication CPU 11 (step S108) and an acknowledgement signal is issued (step S109). This transfers the old communication to a new communication.

In the new communication, the levels of terminals P23 through P29 are inputted at step S110, and the states of the switches are memorized in the internal RAM 30b (step S111).

Thereafter, the state of the power zoom switch SWPZ1 is determined to check the power zoom mode or the manual zoom mode at step S112. If the power zoom switch SWPZ1 is turned OFF, the mode is the manual zoom mode, so that the power hold demand bit (flag) is set to 0 to stop the supply of power to the PZ motor 34. Thereafter, control proceeds to step S116.

If the power zoom switch SWPZ1 is turned ON, the mode is the power zoom mode. Accordingly, the levels of terminals P21 through P29 are inputted to check the states of the switches relating to the zooming operation (step S114). If the levels of all of the terminals P21 through P29 are "H", since no operation for the power zooming is effected, the power hold demand bit is set to 0. Thereafter, control proceeds to step S116.

If the level of any of the terminals P21 through P29 is "L", since the switch connected to the associated terminal relating to the power zooming is turned ON, the power hold demand bit is set to 1 to supply the PZ motor 34 with power (step S115). Thereafter, control proceeds to step S116.

At step S116, a constant image magnification flag FCONST is set to 0. Then, control proceeds to step S117. The constant image magnification flag FCONST detects whether the constant image magnification mode is set. In the illustrated embodiment, the constant image magnification mode referred to means a mode in which when an object of an object distance D is in focus at a specific focal length f, even if there is a small change ΔD in the object distance, the power zooming is controlled to adjust the focal length f' to thereby satisfy the following relationship;

    D/f=(D+ΔD)/f'

At step S117, it is determined whether the power zoom switch SWPZ2 is turned ON. If the power zoom switch SWPZ2 is turned ON, the constant magnification flag FCONST is set to 1, and then, control proceeds to step S119. Conversely, if the power zoom switch SWPZ2 is not turned ON, control directly proceeds to step S119, without setting the constant magnification flag FCONST to 1.

After that, at step S119, serial interruption is permitted. Thereafter, a timer operation is set to intermittently perform the routine of steps S110 through S122 (steps S120 and S121) at 125 ms cycle. Thereafter, the operation stops at step S122. The lens CPU 30 performs the operations of steps S110 through S122 every 125 ms, in accordance with the setting of the timer operation.

Serial Interruption of Lens CPU

FIGS. 15A-15C show a flow chart for the new communication operation when the serial communication is interrupted by the indication CPU 11 of the camera body 1. When the indication CPU 11 causes the level of terminal DATA to fall to "L", the lens CPU 30 enters the new communication operation.

First, the lens CPU 30 prohibits the timer interruption for 10 ms timer, and the 125 ms timer and the serial interruption (steps S130 and S131). Note that the 10 ms timer interruption is a power zoom control operation, in which when serial interruption is permitted, the power zooming is controlled at an interval of 10 ms.

Thereafter, the mode is switched to the SCK output mode, in which the clock signal is outputted from the lens CPU 30 to output the serial clock signal to the terminal SCK (step S132). Communication with the camera body 1 is synchronously carried out with the clock signal outputted from the photographing lens 2.

At step S133, a command code from the indication CPU 11 is inputted.

Thereafter, it is determined whether a 2/4 code of the command code input (step S134). The 2/4 code means a first four bits, of which two bits are always "H" and the remaining bits (two bits) are always "L". If these requirements are not satisfied, no operation is performed, as an input error of the command code, and control jumps to step S167. At step S167, the mode is switched to the SCK input mode, in which the serial clock is inputted from the camera body side, as shown in FIG. 15C. Thereafter, the 10 ms timer interruption and the 125 ms timer interruption and the serial interruption are permitted (steps S168 and S169). At step S170, if the stop flag FSTOP is set to 0, control is directly returned. But, if the stop flag FSTOP is set to 1, control is returned to step S120 of the CPU main routine shown in FIG. 14, after the stop flag FSTOP is set to 1 (step S171).

If the 2/4 code is correct, it is determined whether the command code is the data demand signal at step S135. If the command code is the data demand signal, the acknowledgement signal is outputted to calculate the demanded data or to input the data of the code plate and the switches etc., so as to memorize the data into the internal RAM (steps S136 through S138).

The memorized data is serially outputted synchronously with the SCK clock signal at step S139. Upon completion of the output of the memorized data, an acknowledgement signal is outputted to complete the data transfer (steps S138-2, S139 and S140). Thereafter, control proceeds to step S167.

If the first four bits are not the command code, then the code is checked to see if it is 90H, 91H, 92H, 93H, the sleep code or the test code (steps S141 through S147, step 152, step 157, step S160 and step S165).

If the command code is code 90H (lens accommodation), the acknowledgement signal is sent to the indication CPU 11 (step S142). Thereafter, the present focal length data is sent from the zoom code plate 37 to the indication CPU 11 (step S143). Upon completion of the feeding of the focal length data to the indication CPU 11, an acknowledgement signal is outputted to accommodate or retract the photographing lens (steps S144 and S145). Thereafter, control proceeds to step S167 (FIG. 15C).

If the command code is code 91H (lens return), the receipt acknowledgement signal is sent to the indication CPU 11 (step S148). Thereafter, the focal length data before accommodation is inputted from the indication CPU 11 (steps S149). Upon completion of the inputting of the focal length data before accommodation, an acknowledgement signal is outputted to finish the input of the focal length data before accommodation (step S150). Thereafter, the PZ motor 34 is driven to set the focal length to be the focal length before accommodation at step S151. Thereafter, control proceeds to step S167.

If the command code is code 92H (power hold OFF), a receipt acknowledgement signal is outputted at step S153. Thereafter, the power hold demand bit PHbit is set to 1 (step S154), and the 10 ms timer starts to permit the 10 ms timer interruption (steps S155 and S156). Thereafter, control proceeds to step S167.

If the command code is code 93H (power hold OFF), the acknowledgement signal is output (steps S157 and S158), and the power hold bit is set to 0 (step S159). Thereafter, control proceeds to step S167.

If the command code is none of the codes 90H, 91H, 92H and 93H, it is checked to see if it is a sleep code C1H at step S160. If the command code is the sleep code C1H, a receipt acknowledgement signal is outputted to change the mode, to the SCK input mode in which the level of the terminal CE falls to "L" (steps S161 and S162). Thereafter, the STOP signal generating circuit 69 is set at step S163, and then, control stops (step S164). The sleep code C1H is set to be the second bit of a one byte signal, so that when the second bit is "H", the sleep code C1H is obtained.

If the command code is not the sleep code C1H, it is determined whether a command code is the test code FXH at step S165. If the command code is the test code FXH, the test operation is performed at step S166, and then, control proceeds to step S167. If the command code is not the test code FXH, control skips go to step S166 to step S167. The test mode is not used during the taking of a picture, but is used to effect a predetermined data communication without mounting the photographing lens to the camera body, for example upon assembly of the lens or adjustment thereafter, etc.

At step S167, the mode is changed to the SCK input mode, in which the clock signal can be received from the indication CPU 11. Thereafter, the serial interruption, the 10 ms timer interruption and the 125 ms timer interruption are permitted (steps S168 and S169).

Thereafter, at step S170, it is determined whether the stop flag FSTOP is set to 1. If FSTOP is set to 1, it is set to 0 (step S171). Control is then returned to step S120 of the main routine of the lens CPU. Conversely, if FSTOP is set to 0 at step S170, control is returned.

As can be understood from the above discussion, according to the present invention, since the lens CPU can set the data asynchronously with the clock signal of the camera body, it is not necessary to set the data at a constant interval determined by the camera body.

Furthermore, since the initial data of the lens is set by hardware into the shift register 56 of the lens interface 41 and is successively outputted therefrom, the lens CPU 30 can perform the necessary arithmetic operations during the setting and outputting of the initial data of the lens, thus resulting in a reduction of the time necessary for transferring lens data.

It is possible to mount a conventional lens or an old AE lens to the camera body 1 to which the present invention is applied to take a picture. It is also possible to mount the photographing lens 2 to a conventional camera body.

As can be seen from the above discussion, according to the present invention, since the input and output means for setting the lens data asynchronously with the clock signal of the camera body is provided in the photographing lens, the data can be set independently of the time determined by the control means of the camera body.

In addition, even if the camera body is an old type, dissimilar to the herein disclosed invention, having the system for interchanging information with the lens above, the lens can transfer initial value lens data and certain calculated initial value lens data to the camera body through an input and output means. The camera body applied in this invention can also be attached to an old type of photographing lens.

According to the example of present invention, information can be transferred by serial communication in accordance with the clock signals output from a camera body in the same way as before. When the circuit installed in the lens interface 41 is not being operated, it is possible to interchange information between lens CPU 30 and camera body 1 (indication CPU 11), and it is also possible to calculate data and withdraw some specific data to be transferred to the camera body in accordance to the order of the camera body.

The photographing lens in the example comprises an information processing means, an input and output means which determines lens data without regard to the clock signals output by the clock means of the camera body, and a switching means which enables the camera body to interchange information with the photographing lens without passing through the input and output means. The camera body in the example comprises an information processing means which interchanges information not only with the herein disclosed photographing lens through the input and output means but also with an old type of photographing lens by having direct contact with its information processing means. Therefore, the time for interchanging data can be reduced as only some of the specific data can be transferred. The burden on the camera body is therefore reduced due to the fact that the information processing means installed in the photographing lens plays some of the roles that the information processing means installed in the camera body used to deal in by the order of the camera body.

As the camera body can be used with a former type of photographing lens, and the photographing lens can also be used with a former type of camera body, they have a high potential for general use. 

We claim:
 1. A camera system having a camera body and a photographing lens that is detachably attached to said camera body, said photographing lens comprising:means for calculating predetermined lens data; information processing means for interchanging data with said camera body; initial value lens data determining means for determining proper initial value lens data; timing control means for outputting clock pulses; input and output means that has input and output means to which said initial value lens data and said predetermined lens data calculated by said calculating means are loaded, said loaded data being transferred to an input and output means in a camera body in accordance with clock pulses output from said camera body; means for loading said initial value lens data and said calculated predetermined lens data to said input and output means in accordance with said clock pulses; and, means for connecting said information processing means, without passing through a memory when said initial value lens data has been transferred from said input and output means to said camera body.
 2. A photographing lens which is detachably attached to a camera body, comprising:lens information processing means that function to calculate predetermined lens data and also functions for inputting and outputting data to and from said camera body; means for determining specific initial value lens data; clock means for outputting clock pulses; input and output means that has a memory to which said specific initial value lens data and said calculated predetermined lens data are loaded, said input and output means transferring said data loaded in said memory to said camera body by synchronizing said clock pulses outputted from a clock means installed in said camera body; means for loading said specific initial value lens data and said calculated predetermined lens data to said memory in accordance with clock pulses of either said clock means or a clock means installed in said camera body; means for detecting a completion of said loading of said specific initial value lens data and said calculated predetermined lens data to said camera body; and, means for connecting said lens information processing means to said camera body without passing through said memory upon detecting said completion of said loading of said specific initial value lens data and said calculated predetermined lens data to said camera body. 